The present invention relates to a method and/or architecture for implementing active bias networks generally and, more particularly, an active bias network configured to increase Third-Order Intercept, the 1 dB (decibel) compression point, and improve noise performance of an integrated circuit (IC) amplifier. The present invention may also provide a simplified method of packaging.
Referring to FIG. 1, a typical amplifier 10 that may be used for biasing is shown. The amplifier 10 implements a resistor string RA and RB for biasing. The resistor string RA and RB provides a correct base (or gate voltage) for a desired device current. However, the resistor string (or divider) RA and RB does not provide temperature or process variation correction.
Referring to FIG. 2, a typical biased amplifier circuit is shown. The amplifier 20 includes a bias network of a number of resistors R1, R2, R3, R4, and R5, a transistor Q1, a transistor Q2 and a capacitor C1. The amplifier 20 includes the bias network to provide temperature and process variation correction. However, the bias network does not correct for the non-linearity of the network.
The present invention concerns an apparatus comprising an amplifier and a circuit. The amplifier may be configured to amplify an input signal. The circuit may be configured to (i) control the amplifier, (ii) compensate for non-linear characteristics of the amplifier and (iii) increase the third-order intercept (TOI).
The objects, features and advantages of the present invention include providing a method and/or architecture for active bias networks that may (i) improve the third-order intercept (TOI) (ii) improve noise performance of an integrated circuit amplifier, (iii) improve the 1 dB compression point without the use of external components, (iv) implement a three terminal integrated circuit and/or (v) be implemented in a low cost package.